With each new generation of semiconductor memory, the size and density of the memory array increases. For example, when moving from a 4Mb technology to a 16Mb design, the array area must be increased in order to accommodate the additional memory cells. Increasing the array size, however, adversely effects certain electrical parameters required for optimal circuit performance.
In particular, increasing the size of the memory array leads to a problem known as "resistance droop". In the memory array, long interconnect wires are used to carry voltages across the memory array. When a voltage source is connected to a long interconnect wire, a voltage drop is created on the interconnect wire due to the resistance of the interconnect wire. More specifically, points on the interconnect wire which are located far from the voltage source have a lower voltage potential than those which are located near the voltage source. This voltage differential in the memory array can adversely effect circuit performance and circuit yield.
Accordingly, a need exists for an efficient way to design and fabricate integrated circuits having memory arrays with reduced "resistance droop."